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  this is information on a product in full production. october 2012 doc id 15540 rev. 12 1/29 1 L5150GJ 5 v low dropout voltage regulator datasheet ? production data features operating dc supply voltage range 5.6 v to 40 v low dropout voltage low quiescent current consumption precision output voltage 5 v +/- 2% reset circuit sensing the output voltage programmable reset pulse delay with external capacitor adjustable reset threshold early warning very wide stability range with low value output capacitor thermal shutdown and short-circuit protection wide temperature range (t j = -40c to 150c) enable input for enabling / disabling the voltage regulator description L5150GJ is a low dropout linear regulator with microprocessor control functions such as power on reset, low voltage reset, early warning, on/off control. typical quiescent current is 55 a in very low output current mode and enabled regulator. it drops to 5 a with not enabled regulator. on chip trimming results in high output voltage accuracy (2%). accuracy is kept over wide temperature range, line and load variation. early warning circuit monitors the input voltage and compares it with an internal voltage reference. output voltage reset threshold can be adjusted down to 3.5 v by means of an external voltage divider. the maximum input voltage is 40 v. the max output current is internally limited. internal temperature protection disables the voltage regulator output. in addition, only low-value ceramic capacitor on output is required for stability. max dc supply voltage v s 40 v max output voltage tolerance v o +/-2% max dropout voltage v dp 500 mv output current i o 150 ma quiescent current i qn 5 a (1) 55 a (2) 1. typical value with regulator disabled. 2. typical value with regulator enabled. 3rzhu662 *$3*3 table 1. device summary package order codes tube tape & reel powersso-12 L5150GJ L5150GJtr www.st.com
contents L5150GJ 2/29 doc id 15540 rev. 12 contents 1 block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 powersso-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 powersso-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L5150GJ list of tables doc id 15540 rev. 12 3/29 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. powersso-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of figures L5150GJ 4/29 doc id 15540 rev. 12 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. output voltage vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. output voltage vs. v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. output voltage vs. v en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. drop voltage vs. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. current consumption vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 8. current consumption vs. output current (at light load condition). . . . . . . . . . . . . . . . . . . . . 11 figure 9. current consumption vs. input voltage (io = 0.1 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. current consumption vs. input voltage (io = 75 ma). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. current limitation vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. current limitation vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. short-circuit current vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14. short-circuit current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15. v en_high vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. v en_low vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17. v rhth vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 18. v rlth vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 19. v ewi_thh vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 20. v ewi_thl vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 21. i cr vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 22. i dr vs. t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 23. psrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 24. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 25. stability region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 26. maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 27. reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 28. early warning time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 29. powersso-12 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 30. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20 figure 31. powersso-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 21 figure 32. thermal fitting model of vreg in powersso-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 33. powersso-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 34. powersso-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 35. powersso-12 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L5150GJ block diagram and pins description doc id 15540 rev. 12 5/29 1 block diagram and pins description figure 1. block diagram figure 2. configuration diagram (top view)  /rz9 ro wdjh 5hvhw  9v 9r 67$57  83 92/7$*( 5()(5(1&( 5hv 9fu (: l (: r &x u u h q w olp lw hu 3rz hu 'ulyhu 7khup do 6kxw grz q 5hv$gm *1' 5hvhw  $g m x vw de o h 7ku hvkro g (q  /rz9 ro wdjh 5hvhw  9v 9r 67$57  83 92/7$*( 5()(5(1&( 5hv 9fu (: l (: r &x u u h q w olp lw hu 3rz hu 'ulyhu 7khup do 6kxw grz q 5hv$gm *1' 5hvhw  $g m x vw de o h 7ku hvkro g (q *$3*36 7$% 6xevwudwh               *$3*36
block diagram and pins description L5150GJ 6/29 doc id 15540 rev. 12 table 2. pins description pin name function 1r es_adj reset adjustable threshold. connected to an appropriate external voltage divider, it allows to properly set the reset threshold down to 3.5 v. connect to gnd if not needed. 2r es reset output. internally connected to vo through a 20 k pull-up resistor. this pin is pulled low when v o L5150GJ electrical specifications doc id 15540 rev. 12 7/29 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the table 3: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.2 thermal data table 3. absolute maximum ratings symbol parameter value unit v sdc dc supply voltage -0.3 to 40 v i sdc input current internally limited v odc dc output voltage -0.3 to 6 v i odc dc output current internally limited v od res open drain output voltage r es -0.3 to v odc + 0.3 v i od res open drain output current r es internally limited v res_ad j v res_adj voltage -0.3 to v odc + 0.3 v v od ewo open drain output voltage ew o -0.3 to v odc + 0.3 v i od ewo open drain output current ew o internally limited v cr v cr voltage -0.3 to v o + 0.3 v v ewi early warning input voltage -0.3 to 40 v v en enable input -0.3 to 40 v t j junction temperature -40 to 150 c v esd hbm esd hbm voltage level (hbm-mil std 883c) +/- 2 kv v esd cdm esd cdm voltage level (cdm- ) +/- 750 v table 4. thermal data (1) 1. the values quoted are for pcb 77 mm x 86 mm x 1.6 mm, fr4, double copper layer with single heatsink layer, copper thickness 70 m, thermal vias, copper area 2 cm 2 . symbol parameter value unit r thj-case thermal resistance junction to case: powersso-12 20 k/w r thj-amb thermal resistance junction to ambient: powersso-12 52 k/w
electrical specifications L5150GJ 8/29 doc id 15540 rev. 12 2.3 electrical characteristics values specified in this section are for v s = 5.6 v to 31 v, t j = -40 c to +150 c unless otherwise stated. table 5. general pin symbol parameter test condition min. typ. max. unit v o v o_ref output voltage v s = 8 v to 18 v, i o = 8 ma to 150 ma 4.9 5.0 5.1 v v o v o_ref output voltage v s = 5.6 v to 31 v, i o = 8 ma to 150 ma 4.85 5.0 5.15 v v o v o_ref output voltage v s = 5.6 v to 31 v, i o = 0.1 ma to 8 ma 4.75 5.0 5.25 v v o i short short-circuit current v s = 13.5 v 0.65 0.95 1.25 a v o i lim output current capability (1) v s = 13.5 v 280 470 660 ma v s , v o v line line regulation voltage v s = 6 v to 28 v, i o = 30 ma 40 mv v o v load load regulation voltage v s = 8 v to 18 v, i o = 8 ma to 150 ma 55 mv v s = 13.5 v, t j = 25 c, i o = 8 ma to 150 ma 40 v s , v o v dp drop voltage (2) i o = 150 ma 500 mv v s , v o svr ripple rejection f r = 100 hz (3) 60 db v o i oth_h normal consumption mode output current v s = 8 v to 18 v 8 ma v o i oth_l very low consumption mode output current v s = 8 v to 18 v 1.1 ma v o i oth_hyst output current switching threshold hysteresis v s = 13.5 v, t j = 25 c 0.8 ma v s , v o i qs current consumption with regulator disabled i qs = i vs ? i o v s = 13.5 v, e n = low 510a v s , v o i qn_1 current consumption with regulator enabled i qn_1 = i vs ? i o v s = 13.5 v, i o = 0.1 ma to 1 ma, e n = high tj = 25 c 55 80 a v s = 13.5 v, i o = 0.1 ma to 1 ma, e n = high 95 v s , v o i qn_150 current consumption with regulator enabled i qn_150 = i vs ? i o v s = 13.5 v, i o = 150 ma, e n = high 3.2 4.2 ma
L5150GJ electrical specifications doc id 15540 rev. 12 9/29 t w thermal protection temperature 150 190 c t w_hy thermal protection temperature hysteresis 10 c 1. measured output current when the output voltage has dropped 100 mv from its nominal value obtained at 13.5 v and i o = 75 ma. 2. vs - v o measured dropout when the output voltage has dr opped 100 mv from its nominal value obtained at 13.5 v and i o = 75 ma. 3. guaranteed by design. table 6. reset pin symbol parameter test condition min. typ. max. unit r es v res_l reset output low voltage rext = 5 kw, v o > 1 v 0.4 v r es i res_lkg reset output high leakage current v res = 5 v 1 a r es r res pull up internal resistance versus v o 10 20 40 k r es v o_th v o out of regulation threshold v res_adj < 0.2 v, v o decreasing 6810 % below v o_ref r es_adj v res_adj reset adjustable switching threshold 2.35 2.5 2.65 v r es_adj v res_adjl reset adjustable low voltage 0.4 0.9 1.3 v r es_adj i res_adj_lkg reset adjustable leakage current v res_adj = 2.5 v -1 1 a v cr v rlth reset timing low threshold v s = 13.5 v 15 18 22 % v o_ref v cr v rhth reset timing high threshold v s = 13.5 v 47 50 53 % v o_ref v cr i cr charge current v s = 13.5 v 10 20 30 a v cr i dr discharge current v s = 13.5 v 10 20 30 a r es t rr reset reaction time 2 s r es t rd reset delay time v s = 13.5 v, ctr = 1000 pf 2411ms table 5. general (continued) pin symbol parameter test condition min. typ. max. unit
electrical specifications L5150GJ 10/29 doc id 15540 rev. 12 table 7. early warning pin symbol parameter test condition min. typ. max. unit e wi v ewi_thl ew input low threshold voltage 2.35 2.50 2.65 v ew i v ewi_thh ew input high threshold voltage 2.42 2.57 2.72 v ew i v ewi_thhyst ew input threshold hysteresis 70 mv ew i i ewi_lkg ew input leakage current v ewi = 2.5 v, v s >4v -1 1 a ew o r ewo pull up internal resistance versus v o 10 20 40 k ew o v ewo_lv ew output low voltage (with external pull up) v ewi < 2.35 v, v s >4v, r ext = 5 k 0.4 v ew o i ewo_lkg ew output leakage current v ewo = 5 v 1 a table 8. enable pin symbol parameter test condition min. typ. max. unit e n v en_low e n input low voltage 1 v e n v en_high e n input high voltage 3 v e n v en_hyst e n input hysteresis 500 mv e n i _leak pull-down current v en = 5 v 1.8 10 a
L5150GJ electrical specifications doc id 15540 rev. 12 11/29 2.4 electrical characteristics curves figure 3. output voltage vs. t j figure 4. output voltage vs. v s figure 5. output voltage vs. v en figure 6. drop voltage vs. output current figure 7. current consumption vs. output current figure 8. current consumption vs. output current (at light load condition) 9rbuhi 9                      7m ?& ,r p$ 9v 9 *$3*&)7 9ruhi 9 *$3*&)7              9 6  9 ,r p$ 7f ?& 9rbuhi 9                      9h q 9 9v 9 7f  ?& *$3*36 9gs 9                        ,r p$ 7m ?& 7m ?& *$3*&)7 ,tq p$                     ,r p$ 9v 9 7m ?& (q +l j k *$3*36 *$3*&)7 ,r p$              9v 9 ,tq p$
electrical specifications L5150GJ 12/29 doc id 15540 rev. 12 figure 9. current consumption vs. input voltage (io = 0.1 ma) figure 10. current consumption vs. input voltage (io = 75 ma) figure 11. current limitation vs. t j figure 12. current limitation vs. input voltage figure 13. short-circuit current vs. t j figure 14. short-circuit current vs. input voltage ,tq ?$                       9v 9 *$3*&)7 ,tq p$                       9v 9 *$3*36 (q +ljk ,olp p$                      7m ?& 9v 9 *$3*&)7 *$3*&)7 ,olp p$                       9v 9 7m ?& 7m ?& ,vkruw p$                       7m ?& 9v 9 *$3*&)7 *$3*&)7 ,vkruw p $                        9v 9 7m ?& 7m ?&
L5150GJ electrical specifications doc id 15540 rev. 12 13/29 figure 15. v en_high vs. t j figure 16. v en_low vs. t j figure 17. v rhth vs. t j figure 18. v rlth vs. t j figure 19. v ewi_thh vs. t j figure 20. v ewi_thl vs. t j *$3*36 9hqbkljk 9                      7m ?& 9v 9w r9 *$3*36 9hqborz 9                      7m ?& 9v 9wr9 9ukwk 9rbuhi                      7m ?& 9v 9wr9 *$3*&)7                      7m ?& 9uowk 9rbuhi 9v 9wr9 *$3*&)7 9hzlbwkk 9                      7m ?& 9v 9wr9 *$3*&)7 9hzlbwko 9                      7m ?& 9v 9wr9 *$3*&)7
electrical specifications L5150GJ 14/29 doc id 15540 rev. 12 figure 21. i cr vs. t j figure 22. i dr vs. t j figure 23. psrr ,fu ?$                      7m ?& 9v 9wr9 *$3*&)7 ,gu ?$                      7m ?& 9v 9wr9 *$3*&)7               )5(48(1&<>.+]@ 3655>g%@ &r q) *$3*&)7
L5150GJ application information doc id 15540 rev. 12 15/29 3 application information 3.1 voltage regulator the voltage regulator uses a p-channel mos transistor as a regulating element. with this structure a very low dropout voltage at current up to 150 ma is obtained. the output voltage is regulated up to input supply voltage of 40 v. the high-precision of the output voltage (2%) is obtained with a pre-trimmed reference voltage. the voltage regulator automatically adapts its own quiescent current to the output current level. in light load conditions the quiescent current goes down to 55 a only (low consumption mode). this procedure features a certain hysteresis on the output current (see figure 8 ). short-circuit protection to gnd and a thermal shutdown are provided. figure 24. application schematic the input capacitor f is necessary as backup supply for negative pulses which may occur on the line. the second input capacitor nf is needed when the c 1 is too distant from the v s pin and it compensates smooth line disturbances. the c 0 ceramic capacitor, connected to the output pin, is for bypassing to gnd the high-frequency noise and it guarantees stability even during sudden line and load variations. suggested value is nf ? with . stability region is reported in figure 25 . &r 9 %$77 /*- 567 9fu 567b$'- (:r (:l 9v *1' (q 9r &  &  5 5 5 (: 5 (: *$3*36 c 1 100 = esr 100
application information L5150GJ 16/29 doc id 15540 rev. 12 figure 25. stability region ? figure 26. maximum load variation response                           (65 2kp  &r ?)  (65plq 67$%,/,7<5(*,21 817(67('5(*,21 *$3*36 note: the curve which describes the minimum esr is derived from characterization data on the regulator with connected ceramic capacitors which feature low esr values (at 100 khz). any capacitor with further lower esr than the given plot value must be evaluated in each and every case. v o = 50 mv/div i o = 50 ma/div v s = 13.5 v i o = 8 to 150 ma t c =25c c o = 220 nf
L5150GJ application information doc id 15540 rev. 12 17/29 3.2 reset the reset circuit monitors the output voltage v o . if the output voltage becomes lower than v o_th then r es goes low with a delay time (t rr ). when the output voltage becomes higher than v o_th then r es goes high with a delay time t rd . this delay is obtained by 32 periods of oscillator. the oscillator period is given by: equation 1 t osc = [(v rhth - v rlth ) x c tr ] / i cr + [(v rhth - v rlth ) x c tr ] / i dr where: i cr = 20 a is an internally generated charge current, i dr = 20 a is an internally generated discharge current, v rhth = 2.5 v (typ) and v rlth = 0.9 v (typ) are two voltage thresholds, c tr is an external capacitor put between v cr pin and gnd.
application information L5150GJ 18/29 doc id 15540 rev. 12 reset pulse delay t rd is given by: equation 2 t rd = 32 x t osc the output voltage reset threshold can be adjusted via an external voltage divider r 1 + r 2 (r 1 connected between r es_adj and v 0 , r 2 connected between r es_adj and gnd) according to the following formula: equation 3 v thre = [(r 1 + r 2 ) / r 2 ] * v res_adj the output voltage reset threshold can be decreased down to 3.5 v. if it is needed to maintain it to its default value (8% below v o_ref typical), it is enough to connect the r es_adj pin directly to gnd. figure 27. reset time diagram 9 r 9 fu 5 hv w uu w uu 7 26& w ug  7 26& 9 rxwbwk 9 5kwk 9 5owk *$3*36
L5150GJ application information doc id 15540 rev. 12 19/29 3.3 early warning this circuit compares the ew i input signal with the internal voltage reference (typically 2.5 v). the use of an external voltage divider makes the comparator very flexible in the application. this function can be used to supervise the supply input voltage either before or after the protection diode and to give additional information to the microprocessor such as low voltage warnings. figure 28. early warning time diagram 3.4 enable L5150GJ is also provided with an enable input, an high signal switches the regulator on. when the enable pin is set to low the output is switched-off and the current consumption of the device is 5 a typical. w (:l w (:r (zlbwkbkljk (zlbwkborz +,*+ /2: *$3*&)7
package and pcb thermal data L5150GJ 20/29 doc id 15540 rev. 12 4 package and pcb thermal data 4.1 powersso-12 thermal data figure 29. powersso-12 pc board 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area = 77 mm x 86 mm, pcb thickness =1.6 mm, cu thickness = 70 m (front and back side) thermal vias separation 1.2 mm, thermal via diameter 0. 3 mm +/- 0.08 mm, cu thickness on vias 25 m, footprint dimension 4.1 mm x 6.5 mm ). figure 30. r thj-amb vs pcb copper area in open box free air condition . *$3*&)7 57+mbdpe ?.:           3&%&xkhdwvlqnduhd fpa *$3*36
L5150GJ package and pcb thermal data doc id 15540 rev. 12 21/29 figure 31. powersso-12 thermal impeda nce junction ambient single pulse equation 4: pulse calculation formula where = t p /t figure 32. thermal fitting model of vreg in powersso-12           7lph v =7+ ?&: &x fp &x fp &x irrwsulqw ("1($'5 z th r th z thtp 1 ? () + ? = *$3*&)7
package and pcb thermal data L5150GJ 22/29 doc id 15540 rev. 12 table 9. powersso-12 thermal parameter area (cm 2 )footprint28 r1 (k/w) 1.53 r2 (k/w) 3.21 r3 (k/w) 5.2 r4 (k/w) 7 7 8 r5 (k/w) 22 15 10 r6 (k/w) 26 20 15 c1 (w.s/k) 0.00004 c2 (w.s/k) 0.0016 c3 (w.s/k) 0.08 c4 (w.s/k) 0.2 0.1 0.1 c5 (w.s/k) 0.27 0.8 1 c6 (w.s/k) 3 6 9
L5150GJ package and packing information doc id 15540 rev. 12 23/29 5 package and packing information 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 powersso-12 mechanical data figure 33. powersso-12 package dimensions *$3*&)7
package and packing information L5150GJ 24/29 doc id 15540 rev. 12 table 10. powersso-12 mechanical data symbol millimeters min. typ. max. a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k0 8 x 1.900 2.500 y 3.600 4.200 ddd 0.100
L5150GJ package and packing information doc id 15540 rev. 12 25/29 5.3 powersso-12 packing information figure 34. powersso-12 tube shipment (no suffix) figure 35. powersso-12 tape and reel shipment (suffix ?tr?) % $ & $ooglphqvlrqvduhlqpp %dvhtw\  %xontw\  7xehohqjwk ?  $ % & ?  *$3*36   %dvhtw\  %xontw\  $ pd[  % plq  & ?  )  *   1 plq  7 pd[  5hhoglphqvlrqv 7dshglphqvlrqv $ffruglqjwr(ohfwurqlf,qgxvwulhv$vvrfldwlrq (,$ 6wdqgduguhy$ )he $ooglphqvlrqvduhlqpp 7dsh zlgwk :  7dsh krohvsdflqj 3 ?  &rpsrqhqwvsdflqj 3  +rohgldphwhu ' ?  +rohgldphwhu ' plq  +rohsrvlwlrq ) ?  &rpsduwphqwghswk . pd[  +rohvsdflqj 3 ?  7r s fryhu wdsh (qg 6wduw 1rfrpsrqhqwv 1rfrpsrqhqwv &rpsrqhqwv ppplq ppplq (psw\frpsrqhqwvsrfnhwv vdohgzlwkfryhuwdsh 8vhugluhfwlrqriihhg *$3*36
revision history L5150GJ 26/29 doc id 15540 rev. 12 6 revision history table 11. document revision history date revision changes 09-aug-2007 1 initial release. 06-mar-2008 2 modified description on cover page. updated table 5.: general : ? changed v o_ref , vline, vload test conditions ? added notes to ilim and vdp parameters ? added i oth_h, i oth_l, i oth parameters. updated table 6.: reset : ? added v res_adj parameter ? changed v rlth values (min./ typ./ max.) from 17/20/23 to 20/23/26 (% v o_ref ). updated table 8.: enable : ? changed v en_hyst typ. value from 800 mv to 500 mv ? changed i _leak typ. value from 3 a to 1.8 a. modified section 3.2: reset . 09-may-2008 3 updated table 5.: general : ? changed i lim values (min./typ./max.) from 0.7/1/1.30 a to 280/470/660 ma. ?v o_ref parameter : updated io test condition old -> i o = 0.1 ma to i0ma new -> i o = 0.1 ma to 8 ma. 13-oct-2008 4 updated table 5.: general : ?v load parameter : updated i o test condition old -> i o = 5 ma to i50 ma new -> i o = 8 ma to 150 ma
L5150GJ revision history doc id 15540 rev. 12 27/29 15-apr-2009 5 updated corporate template updated figure 2: configuration diagram (top view) table 2: pins description ? added new row table 4: thermal data ?r thj-amb : changed value ? updated tablefootnote table 5: general ?v load : changed max value for vs = 8 v to 18 v, added new row ?i qn_1 : changed test conditions (added t j = 25 c), added new row table 6: reset ?v rlth : changed min/typ/max value ?v res_adjl: replaced with v rlth , changed parameter table 7: early warning ? updated symbols added figure 3: output voltage vs. t j added figure 4: output voltage vs. v s added figure 5: output voltage vs. v en added figure 6: drop voltage vs. output current added figure 7: current consumption vs. output current added figure 8: current consumption vs. output current (at light load condition) added figure 9: current consumption vs. input voltage (io = 0.1 ma) added figure 10: current consumption vs. input voltage (io = 75 ma) added figure 11: current limitation vs. t j added figure 12: current limitation vs. input voltage added figure 13: short-circuit current vs. t j added figure 14: short-circuit current vs. input voltage added figure 15: v en_high vs. t j added figure 16: v en_low vs. t j added figure 17: v rhth vs. t j added figure 18: v rlth vs. t j added figure 19: v ewi_thh vs. t j added figure 20: v ewi_thl vs. t j added figure 21: i cr vs. t j added figure 22: i dr vs. t j added figure 23: psrr section 3.1: voltage regulator ? updated text ? added figure 24: application schematic ? added figure 26: maximum load variation response section 3.2: reset ? v rlth : changed value from 1.15 v to 0.9 v in equation 1 updated section 3.4: enable added section 4: package and pcb thermal data changed section 5.1: ecopack ? table 11. document revision history (continued) date revision changes
revision history L5150GJ 28/29 doc id 15540 rev. 12 09-jun-2009 6 changed document title table 5: general ?i oth_h , i oth_l : added test condition updated figure 4: output voltage vs. v s section 3.3: early warning ? changed internal voltage reference typical value from 1.23 v to 2.5 v updated figure 31: powersso-12 thermal impedance junction ambient single pulse 04-dec-2009 7 updated features list. updated table 2: pins description . updated section 3.1: voltage regulator . corrected equation 3 on section 3.2: reset . 19-apr-2010 8 updated footnote description of table 4: thermal data . updated figure 30: rthj-amb vs pcb copper area in open box free air condition . updated table 9: powersso-12 thermal parameter . 30-jan-2012 9 updated figure 25: stability region on page 16 . 07-feb-2012 10 modified figure 25: stability region on page 16 . 02-oct-2012 11 updated table 6: reset : ?t rd : updated maximum value 19-sep-2013 12 updated disclaimer. table 11. document revision history (continued) date revision changes
L5150GJ doc id 15540 rev. 12 29/29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com


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